1. Field of the Invention
The present invention relates to a signal processor and an apparatus and method for testing the signal processor.
2. Description of the Related Art
FIG. 1 is a schematic diagram of an integrator circuit. As shown in FIG. 1, the integrator circuit includes an input terminal which receives an input signal Vi to be integrated by the circuit and an output terminal at which the integrated output signal Vo is output from the circuit. Generally, an integrator circuit includes an operational amplifier (op amp) 100, a resistor R connected between the input terminal of the integrator circuit and an inverting terminal of the op amp 100, and a capacitor C connected between the inverting terminal of the op amp 100 and an output terminal of the op amp 100.
The resistance of the resistor R may vary within about 20% of a desired resistance, and the capacitance of the capacitor C may vary within about 10% of a desired capacitance. The error rate of the resistor R and capacitor C is inadequate when the integrator is used in controlling a small or low-level signal.
To solve this problem, a switched capacitor has been used in the integrator. In the switched capacitor, a capacitor and switches replace the resistor R. The switched capacitor integrator may accurately control a low-level signal to output precise results because the error rate of the capacitor is smaller than the error rate of the resistor.
FIG. 2 is a schematic diagram of a switched capacitor integrator circuit. As shown in FIG. 2, the switched capacitor integrator includes an operational amplifier 200, first and second capacitors C1 and C2, switches S1, S2, S3 and S4.
The first capacitor C1 is connected through a switch S2 to an inverting (−) terminal of the op amp 200. First and second switches S1 and S2 are serially connected to first and second ends, respectively, of the first capacitor C1 to thereby allow an input signal to be applied to the inverting (−) terminal of the op amp 200. The third and fourth switches S3 and S4 are connected in parallel to first and second ends, respectively, of the first capacitor to thereby allow a DC reference voltage (Vcom) to be applied to the first capacitor C1. The DC reference voltage (Vcom) is a reference signal for the input signal (Vi). The second capacitor C2 is connected between the inverting (−) terminal and the output terminal of the operational amplifier 200.
FIG. 3 is a timing diagram illustrating timing of two clock signals P1 and P2 used to control the opening and closing of the switches S1, S2, S3 and S4. Referring to FIG. 3, the first, second, third and fourth switches S1, S2, S3 and S4 are turned on/off in response to the first and second clock signals P1 and P2 of FIG. 3. The active status of the first clock signal P1 does not overlap with the active status of the second clock signal P2. The active status of each of the first and second clock signals is alternately repeated as shown in FIG. 3.
The first and third switches S1 and S3 are turned on, i.e., closed, during the active status of the first clock signal P1, and thus the input signal Vi charges the first capacitor C1 during the active status of P1. The second and fourth switches S2 and S4 are turned on during the active status of the second clock signal P2, and thus the charge at the first capacitor C1 is applied to the inverting (−) terminal of the op amp 200 during the active status of P2.
The quantity of the charge applied to the op amp 200 during one period of the first and second clock signals P1 and P2 is substantially constant, and therefore, the capacitor C1 and switches S1, S2, S3 and S4 restrict the movement of the charge, in similar fashion to the resistor R of FIG. 1.
The switched capacitor integrator is used, for example, in a voice codec (coder/decoder), which converts an analog signal to a digital signal, or vice versa. The voice codec can be used in a mobile communication device.
Particularly, the switched capacitor integrator can be used in the analog sigma-delta modulator or an analog filter of the voice codec.
FIG. 4 is a schematic circuit diagram showing a conventional analog sigma-delta modulator.
Referring to FIG. 4, the analog sigma-delta modulator includes a first switched capacitor integrator 400, a second switched capacitor integrator 410 and a comparator 420. The first and second switched capacitor integrators 400 and 410 include a plurality of switches and a plurality of capacitors. The switches are turned on/off in response to the first and second clock signals P1 and P2 of FIG. 3. The capacitors are charged and discharged according to the switching operation of the switches. In addition, the conventional analog sigma-delta modulator may include a digital-to-analog converter that feeds back the signal VREF_TOP or VREF_BOT to the first and second switched capacitor integrators 400 and 410.
The voice codec having the above analog sigma-delta modulator usually has three input lines to which a test signal can be applied. The output signal of the voice codec is compared with predetermined signals so as to test the operation of the voice codec.
When an analog test signal is applied to a first input line, the analog test signal is converted to a digital signal by the sigma-delta modulator of FIG. 4. The output of the sigma-delta modulator of FIG. 4 is used to test the operation of the voice codec.
When an analog test signal is applied to a second input line, the sigma-delta modulator of FIG. 4 outputs a digital signal converted from the analog test signal after considerable time delay. After the test signal is applied to the first input line, charges are accumulated at the capacitors of the sigma-delta modulator of FIG. 4, and then the test signal is applied to the second input line while charges are accumulated at the capacitors of the sigma-delta modulator of FIG. 4, to thereby cause the time delay.
Wait time is required in order to discharge the capacitors, and thus wait time is calculated. Then, the test signal is applied to the second input line after the lapse of the wait time.
However, the capacitors of the conventional analog sigma-delta modulator or analog filter are discharged slowly in response to a clock signal, so the time for discharging the capacitors can be considerable.
Therefore, considerable time delay is caused in testing the voice codec having a plurality of input lines.